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1 for more information www.linear.com/lt6118 typical a pplica t ion fea t ures descrip t ion current sense amplifer, reference and comparator with por the lt ? 6118 is a complete high side current sense device that incorporates a precision current sense amplifer, an integrated voltage reference and a latching comparator. the comparator latch functionality can be enabled or disabled and the comparator can be confgured to reset upon power-on. the input and the open-drain output of the comparator are independent from the current sense amplifer. the comparator trip point and amplifer gain are confgured with external resistors. the overall propagation delay of the lt6118 is typically only 1.4s, allowing for quick reaction to overcurrent condi - tions. the 1mhz bandwidth allows the lt6118 to be used for error detection in critical applications such as motor control. the high threshold accuracy of the comparator , combined with the ability to latch the comparator , ensures the lt6118 can capture high speed events. the lt6118 is fully specifed for operation from C40c to 125c, making it suitable for industrial and automotive applications. the lt6118 is available in the small 8-lead msop and 8-lead dfn packages. fast acting fault protection with power-on reset a pplica t ions n current sense amplifer C fast step response: 500ns C low offset voltage: 200v maximum C low gain error: 0.2% maximum n internal 400mv precision reference n internal comparator C power-on reset capability C fast response time: 500ns C total threshold error: 1.25% maximum n wide supply range: 2.7v to 60v n supply current: 450a n specifed for C40c to 125c temperature range n available in 8-lead msop and 8-lead (2mm 3mm) dfn packages n overcurrent and fault detection n current shunt measurement n battery monitoring n motor control n automotive monitoring and control n industrial control l , lt, ltc, ltm, timerblox, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. response to overcurrent event sensehi senselo outa lt6118 inc 250ma disconnect v + le outc v ? 0.1 3.3v 12v 100 10k *cmh25234b 1k 24.9k 1k 2n2700 6.2v* 6.04k 0.1f irf9640 v out 1.6k 6118 ta01a to load 100nf v load 10v/div i load 200ma/div v outc 5v/div 0v 0v 0ma 6118 ta01b 5s/div 250ma disconnect lt6118 6118f
2 for more information www.linear.com/lt6118 a bsolu t e maxi m u m r a t ings total supply voltage (v + to v C ) ................................. 60v m aximum voltage (senselo, sensehi, outa) ............................... v + + 1v maximum v + C (senselo or sensehi) .................... 3 3v maximum le voltage ................................................ 6 0v maximum comparator input voltage ........................ 6 0v maximum comparator output voltage...................... 60v input current (note 2) .......................................... C 10ma sensehi, senselo input current ....................... 1 0ma differential sensehi or senselo input current .. 2.5ma (note 1) o r d er i n f or m a t ion lead free finish tape and reel part marking* package description specified temperature range lt6118ims8#pbf lt6118ims8#trpbf ltgns 8-lead plastic msop C40c to 85c lt6118hms8#pbf lt6118hms8#trpbf ltgns 8-lead plastic msop C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ amplifer output short-circuit duration (to v C ) .. indefnite o perating temperature range (note 3) l t6118i ................................................ C 40c to 85c l t6118h ............................................. C 40c to 125c specifed temperature range (note 3) l t6118i ................................................ C 40c to 85c l t6118h ............................................. C 40c to 125c maximum junction temperature .......................... 15 0c storage temperature range .................. C 65c to 150c msop lead temperature (soldering, 10 sec) ........ 3 00c p in c on f igura t ion 1 2 3 4 senselo le outc v ? 8 7 6 5 sensehi v + outa inc top view ms8 package 8-lead plastic msop ja = 163c/w, jc = 45c/w top view sensehi v + outa inc senselo le outc v ? dcb package 8-lead (2mm 3mm) plastic dfn 9 3 4 2 1 6 5 7 8 ja = 64c/w, jc = 10c/w exposed pad (pin 9) is v C , pcb connection optional lead free finish tape and reel (mini) tape and reel part marking* package description specified temperature range lt6118idcb#pbf lt6118idcb#trpbf lgnt 8-lead (2mm 3mm) plastic dfn C40c to 85c lt6118hdcb#pbf lt6118hdcb#trpbf lgnt 8-lead (2mm 3mm) plastic dfn C40c to 125c trm = 500 pieces. *temperature grades are identifed by a label on the shipping container. consult ltc marketing for parts specifed with wider operating temperature ranges. consult ltc marketing for information on lead based fnish parts. for more information on lead free part marking, go to: http://www .linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ lt6118 6118f
3 for more information www.linear.com/lt6118 e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v + = 12v, v pullup = v + , v le = 2.7v, r in = 100, r out = r1 + r2 = 10k, gain = 100, r c = 25.5k, c l = c lc = 2pf, unless otherwise noted. (see figure 2) symbol parameter conditions min typ max units v + supply voltage range l 2.7 60 v i s supply current (note 4) v + = 2.7v, r in = 1k, v sense = 5mv 450 a v + = 60v, r in = 1k, v sense = 5mv l 550 650 950 a a le pin current v le = 0v, v + = 60v C100 na v ih le pin input high v + = 2.7v to 60v l 1.5 v v il le pin input low v + = 2.7v to 60v l 0.5 v current sense amplifer v os input offset voltage v sense = 5mv v sense = 5mv l C200 C300 200 300 v v ? v os /?t input offset voltage drift v sense = 5mv l 0.8 v/c i b input bias current (senselo, sensehi) v + = 2.7v to 60v l 60 300 350 na na i os input offset current v + = 2.7v to 60v 5 na i outa output current (note 5) l 1 ma psrr power supply rejection ratio (note 6) v + = 2.7v to 60v l 120 114 127 db db cmrr common mode rejection ratio v + = 36v, v sense = 5mv, v icm = 2.7v to 36v 125 db v + = 60v, v sense = 5mv, v icm = 27v to 60v l 110 103 125 db db v sense(max) full-scale input sense voltage (note 5) r in = 500 l 500 mv gain error (note 7) v + = 2.7v to 12v v + = 12v to 60v, v sense = 5mv to 100mv, ms8 package v + = 12v to 60v, v sense = 5mv to 100mv, dfn package l l C0.2 C0.3 C0.08 0 0 % % % senselo v oltage (note 8) v + = 2.7v, v sense = 100mv, r out = 2k v + = 60v, v sense = 100mv l l 2.5 27 v v output swing high (v + to v outa ) v + = 2.7v, v sense = 27mv l 0.2 v v + = 12v, v sense = 120mv l 0.5 v bw signal bandwidth i out = 1ma i out = 100a 1 140 mhz khz t r input step response (to 50% of final output voltage) v + = 2.7v, v sense = 24mv step, output rising edge v + = 12v to 60v, v sense = 100mv step, output rising edge 500 500 ns ns t settle settling time to 1% v sense = 10mv to 100mv, r out = 2k 2 s lt6118 6118f
4 for more information www.linear.com/lt6118 e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v + = 12v, v pullup = v + , v le = 2.7v, r in = 100, r out = r1 + r2 = 10k, gain = 100, r c = 25.5k, c l = c lc = 2pf, unless otherwise noted. (see figure 2) symbol parameter conditions min typ max units reference and comparator v th(r) (note 9) rising input threshold voltage v + = 2.7v to 60v l 395 400 405 mv v hys v hys = v th(r) C v th(f) v + = 2.7v to 60v 3 10 15 mv comparator input bias current v inc = 0v, v + = 60v l C50 na v ol output low voltage i outc = 500a, v + = 2.7v l 60 150 220 mv mv high to low propagation delay 5mv overdrive 100mv overdrive 3 0.5 s s output fall t ime 0.08 s t reset reset time 0.5 s t rpw minimum le reset pulse width l 2 s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: input and output pins have esd diodes connected to ground. the sensehi and senselo pins have additional current handling capability specifed as sensehi, senselo input current. note 3: the lt6118i is guaranteed to meet specifed performance from C40c to 85c. lt6118h is guaranteed to meet specifed performance from C40c to 125c. note 4: supply current is specifed with the comparator output high. when the comparator output goes low the supply current will increase by 75a typically. note 5: the full-scale input sense voltage and the maximum output current must be considered to achieve the specifed performance. note 6: supply voltage and input common mode voltage are varied while amplifer input offset voltage is monitored. note 7: the specifed gain error does not include the effect of external resistors r in and r out . although gain error is only guaranteed between 12v and 60v, similar performance is expected for v + < 12v, as well. note 8: refer to senselo, sensehi range in the applications information section for more information. note 9: the input threshold voltage which causes the output voltage of the comparator to transition from high to low is specifed. the input voltage which causes the comparator output to transition from low to high is the magnitude of the difference between the specifed threshold and the hysteresis. supply current vs supply voltage start-up supply current input offset voltage vs temperature supply voltage (v) 0 0 supply current (a) 100 200 300 400 600 10 20 30 40 6118 g01 50 60 500 0v v + 5v/div 0a i s 500a/div 10s/div 6118 g02 temperature (c) ?40 input offset voltage (v) 300 200 100 0 ?200 ?100 ?300 80 6118 g03 ?10 20 50 125 110 65 ?25 5 35 95 5 typical units performance characteristics taken at t a = 25c, v + = 12v, v pullup = v + , v le = 2.7v, r in = 100, r out = r1 + r2 = 10k, gain = 100, r c = 25.5k, c l = c lc = 2pf, unless otherwise noted. (see figure 2) typical p er f or m ance c harac t eris t ics lt6118 6118f
5 for more information www.linear.com/lt6118 typical p er f or m ance c harac t eris t ics amplifer offset voltage vs supply voltage amplifer gain error vs temperature offset voltage drift distribution amplifer gain error distribution performance characteristics taken at t a = 25c, v + = 12v, v pullup = v + , v le = 2.7v, r in = 100, r out = r1 + r2 = 10k, gain = 100, r c = 25.5k, c l = c lc = 2pf, unless otherwise noted. (see figure 2) supply voltage (v) 0 ?100 offset voltage (v) ?60 ?20 20 10 20 30 40 6118 g04 50 60 100 ?80 ?40 0 40 80 60 5 typical units offset voltage drift (v/c) 0 percentage of units (%) 2 4 6 8 12 ?1?1.5?2 ?0.5 0 0.5 1 1.5 2 6118 g05 10 gain error (%) 0 percentage of units (%) 5 15 20 25 v sense = 5mv to 100mv ?0.056 ?0.068 6118 g07 10 ?0.048 ?0.052 ?0.060 ?0.064 temperature (c) ?50 ?0.18 gain error (%) ?016 ?0.12 ?0.10 ?0.08 0.02 ?0.04 0 50 75 6118 g06 ?0.14 ?0.02 0 ?0.06 ?25 25 100 125 v sense = 5mv to 100mv r in = 1k r in = 100 temperature (c) ?50 0 v + ? v outa (v) 0.05 0.15 0.20 0.25 0.50 0.35 0 50 75 6118 g08 0.10 0.40 0.45 0.30 ?25 25 100 125 v + = 12v v sense = 120mv v + = 2.7v v sense = 27mv common mode rejection ratio vs frequency amplifer output swing vs temperature frequency (hz) 1 0 common mode rejection ratio (db) 120 100 140 10 100 1k 10k 100k 1m 10m 6118 g09 80 60 40 20 amplifer gain vs frequency step response 0v v sense 100mv/div v outa 1v/div v outc 2v/div v le 5v/div 0v 0v 0v 6118 g11 2s/div r out = 2k 100mv inc overdrive 0v v sense 100mv/div v outa 1v/div v outc 2v/div 0v 0v 6118 g12 2s/div r out = 2k,100mv inc overdrive, v le = 0v step response frequency (hz) 22 gain (db) 28 34 40 46 1k 100k 1m 10m 6118 g10 16 10k i outa = 1ma i outa = 100a g = 100, r out = 10k g = 50, r out = 5k g = 20, r out = 2k lt6118 6118f
6 for more information www.linear.com/lt6118 performance characteristics taken at t a = 25c, v + = 12v, v pullup = v + , v le = 2.7v, r in = 100, r out = r1 + r2 = 10k, gain = 100, r c = 25.5k, c l = c lc = 2pf, unless otherwise noted. (see figure 2) amplifer input bias current vs temperature amplifer step response (v sense = 10mv to 100mv) amplifer step response (v sense = 0mv to 100mv) amplifer step response (v sense = 10mv to 100mv) amplifer step response (v sense = 0mv to 100mv) typical p er f or m ance c harac t eris t ics temperature (c) ?25 input bias current (na) 60 80 100 95 6118 g13 40 20 50 70 90 30 10 0 5 35 65 ?10?40 110 20 50 80 125 sensehi senselo v outa 2v/div v sense 50mv/div 0v 0v 6118 g14 2s/div r in = 100 g = 100v/v v outa 2v/div v sense 50mv/div 0v 0v 6118 g15 2s/div r in = 100 g = 100v/v 0v 0v v outa 1v/div v sense 100mv/div 6118 g16 2s/div r in = 1k r out = 20k g = 20v/v 0v 0v v outa 1v/div v sense 100mv/div 6118 g17 2s/div r in = 1k r out = 20k g = 20v/v comparator threshold distribution comparator threshold vs temperature temperature (c) ?40 comparator threshold (mv) 408 406 404 402 400 398 396 394 392 80 6118 g20 ?10 20 50 125 110 65 ?25 5 35 95 5 typical units comparator threshold (mv) 0 percentage of units (%) 5 15 20 25 399.2 404 6118 g19 10 396 397.6 400.8 402.8 power supply rejection ratio vs frequency frequency (hz) 1 0 power supply rejection ratio (db) 120 100 140 160 10 100 1k 10k 100k 1m 10m 6118 g18 80 60 40 20 lt6118 6118f
7 for more information www.linear.com/lt6118 performance characteristics taken at t a = 25c, v + = 12v, v pullup = v + , v le = 2.7v, r in = 100, r out = r1 + r2 = 10k, gain = 100, r c = 25.5k, c l = c lc = 2pf, unless otherwise noted. (see figure 2) hysteresis distribution hysteresis vs temperature hysteresis vs supply voltage le current vs voltage typical p er f or m ance c harac t eris t ics temperature (c) ?40 comparator hysteresis (mv) 20 18 16 14 12 10 8 6 4 0 2 80 6118 g22 ?10 20 50 125 110 65 ?25 5 35 95 v + (v) 0 14 12 10 8 6 4 2 0 30 50 6118 g23 10 20 40 60 comparator hysteresis (mv) 5 typical units le voltage (v) 0 ?250 le current (na) ?200 ?150 ?100 ?50 50 10 20 30 40 6118 g24 50 60 0 v + = 12v comparator hysteresis (mv) 3 0 percentage of units (%) 5 10 15 20 30 ?40c 25c 125c 4.6 6.2 7.7 9.3 10.9 12.5 6118 g21 14.1 15.7 17.3 25 comparator input bias current vs input voltage comparator input voltage (v) ?20 comparator input bias current (na) ?10 0 10 ?15 ?5 5 0.2 0.4 0.6 0.8 6118 g26 1.0 0 125c 25c ?40c comparator input bias current vs input voltage comparator input voltage (v) ?20 comparator input bias current (na) ?10 0 10 ?15 ?5 5 20 40 6118 g25 60 0 125c 25c ?40c comparator propagation delay vs input overdrive comparator output leakage current vs pull-up voltage comparator output low voltage vs output sink current i outc (ma) 0 0 v ol outc (v) 0.25 0.50 0.75 1.00 1 2 6118 g27 3 125c 25c ?40c comparator output pull-up voltage (v) 0 ?2 outc leakage current (na) 3 8 13 18 23 125c 10 20 30 40 6118 g28 50 60 ?40c and 25c comparator input overdrive (mv) 0 comparator propagation delay (s) 3.0 4.0 5.0 160 6118 g29 2.0 1.0 2.5 3.5 4.5 1.5 0.5 0 40 80 120 200 rising input falling input lt6118 6118f
8 for more information www.linear.com/lt6118 comparator rise/fall time vs pull-up resistor comparator step response (5mv inc overdrive) comparator step response (100mv inc overdrive) typical p er f or m ance c harac t eris t ics performance characteristics taken at t a = 25c, v + = 12v, v pullup = v + , v le = 2.7v, r in = 100, r out = r1 + r2 = 10k, gain = 100, r c = 25.5k, c l = c lc = 2pf, unless otherwise noted. (see figure 2) r c pull-up resistor (k) 1 10 rise/fall time (ns) 100 1000 10000 10 100 1000 6118 g30 v oh = 0.9 ? v pullup v ol = 0.1 ? v pullup 100mv inc overdrive c l = 2pf falling input rising input v inc 0.5v/div 0v v outc 2v/div v le 5v/div 0v 0v 6118 g31 5s/div v + = 5v 0v v inc 0.5v/div v outc 2v/div v le 5v/div 0v 0v 6118 g32 5s/div v + = 5v comparator step response (5mv inc overdrive) comparator step response (100mv inc overdrive) comparator reset response senselo (pin 1): sense amplifer input. this pin must be tied to the load end of the sense resistor. le (pin 2): latch control pin. when high, the comparator latch is enabled. with the comparator latch enabled, the comparator output will latch at a low level once tripped. when the le input is low, the comparator latch is disabled and the comparator functions transparently. outc (pin 3): open-drain comparator output. off-state voltage may be as high as 60v above v C , regardless of v + used. v C (pin 4): negative supply pin. this pin is normally con- nected to ground. inc (pin 5): this is the inverting input of the comparator . the other comparator input is internally connected to the 400mv reference. v inc 0.5v/div 0v v outc 1v/div 6118 g33 5s/div 0v v + = 5v v le = 0v v inc 0.5v/div 0v v outc 1v/div 6118 g34 5s/div 0v v + = 5v v le = 0v 0v v outc 5v/div v le 2v/div 0v 5s/div 6118 g35 p in func t ions lt6118 6118f
9 for more information www.linear.com/lt6118 p in func t ions b lock diagra m 100 outa ? + ? + 7 8 1 6 inc 5 6118 f01 v + v ? v ? v ? v ? v + 3k v + 3k sensehi senselo 100na overcurrent flag 2 le 3 outc 34v 6v v ? 4 400mv reference figure 1. block diagram outa (pin 6): current output of the sense amplifer. this pin will source a current that is equal to the sense voltage divided by the external gain setting resistor, r in . v + (pin 7): positive supply pin. the v + pin can be con - nected directly to either side of the sense resistor, r sense . when v + is tied to the load end of the sense resistor, the sensehi pin can go up to 0.2v above v + . supply current is drawn through this pin. sensehi (pin 8): sense amplifer input. the internal sense amplifer will drive sensehi to the same potential as senselo. a resistor (typically r in ) tied from supply to sensehi sets the output current, i out = v sense /r in , where v sense is the voltage developed across r sense . exposed pad (pin 9, dcb package only): v C . the exposed pad may be left open or connected to device v C . connect- ing the exposed pad to a v C plane will improve thermal management in high voltage applications. the exposed pad should not be used as the primary connection for v C . a pplica t ions i n f or m a t ion the lt6118 high side current sense amplifer provides accurate monitoring of currents through an external sense resistor. the input sense voltage is level-shifted from the sensed power supply to a ground referenced output and is amplifed by a user-selected gain to the output. the output voltage is directly proportional to the current fow - ing through the sense resistor. the lt6118 comparator has a threshold set with a built-in 400mv precision reference and has 10mv of hysteresis. the open-drain output can be easily used to level shift to digital supplies. amplifer theory of operation an internal sense amplifer loop forces sensehi to have the same potential as senselo as shown in figure 2. lt6118 6118f
10 for more information www.linear.com/lt6118 a pplica t ions i n f or m a t ion note that v sense(max) can be exceeded without damag - ing the amplifer, however, output accuracy will degrade as v sense exceeds v sense(max) , resulting in increased output current, i outa . selection of external current sense resistor the external sense resistor, r sense , has a signifcant effect on the function of a current sensing system and must be chosen with care. first, the power dissipation in the resistor should be consid - ered. the measured load current will cause power dissipation as well as a voltage drop in r sense . as a result, the sense resistor should be as small as possible while still providing the input dynamic range required by the measurement. note that the input dynamic range is the difference between the maximum input signal and the minimum accurately repro - duced signal, and is limited primarily by input dc offset of the internal sense amplifer of the l t6118. t o ensure the specifed performance, r sense should be small enough that v sense does not exceed v sense(max) under peak load conditions. as an example, an application may require the maximum sense voltage be 100mv. if this application is expected to draw 2a at peak load, r sense should be set to 50m. once the maximum r sense value is determined, the mini - mum sense resistor value will be set by the resolution or dynamic range required. the minimum signal that can be figure 2. typical connection outa i outa ? + v + c1 sensehi inc 6 7 8 5 6118 f02 v + v + v ? lt6118 senselo le outc 1 2 3 4 v le r c v pullup load v supply v sense r sense overcurrent flag r in + ? *r out = r1 + r2 v ? i sense = v sense r sense r1* r2* c l v out 400mv reference c lc ? + connecting an external resistor, r in , between sensehi and v supply forces a potential, v sense , across r in . a corresponding current, i outa , equal to v sense /r in , will fow through r in . the high impedance inputs of the sense amplifer do not load this current, so it will fow through an internal mosfet to the output pin, outa. the output current can be transformed back into a voltage by adding a resistor from outa to v C (typically ground). the output voltage is then: v out = v C + i outa ? r out where r out = r1 + r2 as shown in figure 2. table 1. example gain confgurations gain r in r out v sense for v out = 5v i outa at v out = 5v 20 499 10k 250mv 500a 50 200 10k 100mv 500a 100 100 10k 50mv 500a useful equations input voltage: v sense = i sense ?r sense voltage gain: v out v sense = r out r in current gain: i outa i sense = r sense r in lt6118 6118f
11 for more information www.linear.com/lt6118 a pplica t ions i n f or m a t ion accurately represented by this sense amplifer is limited by the input offset. as an example, the lt6118 has a maximum input offset of 200v. if the minimum current is 20ma, a sense resistor of 10m will set v sense to 200v. this is the same value as the input offset. a larger sense resis - tor will reduce the error due to offset by increasing the sense voltage for a given load current. choosing a 50m r sense will maximize the dynamic range and provide a system that has 100mv across the sense resistor at peak load (2a), while input offset causes an error equivalent to only 4ma of load current. in the previous example, the peak dissipation in r sense is 200mw. if a 5m sense resistor is employed, then the effective current error is 40ma, while the peak sense voltage is reduced to 10mv at 2a, dissipating only 20mw. the low offset and corresponding large dynamic range of the lt6118 make it more fexible than other solutions in this respect. the 200v maximum offset gives 68db of dynamic range for a sense voltage that is limited to 500mv max. sense resistor connection kelvin connection of the sensehi and senselo inputs to the sense resistor should be used in all but the lowest power applications. solder connections and pc board interconnections that carry high currents can cause sig - nifcant error in measurement due to their relatively large resistances. one 10mm 10mm square trace of 1oz copper is approximately 0.5m. a 1mv error can be caused by as little as 2a fowing through this small interconnect. this will cause a 1% error for a full-scale v sense of 100mv. a 10a load current in the same interconnect will cause a 5% error for the same 100mv signal. by isolating the sense traces from the high current paths, this error can be reduced by orders of magnitude. a sense resistor with integrated kelvin sense terminals will give the best results. figure 2 illustrates the recommended method for connect - ing the sensehi and senselo pins to the sense resistor. selection of external input gain resistor , r in r in should be chosen to allow the required speed and resolution while limiting the output current to 1ma. the maximum value for r in is 1k to maintain good loop stability. for a given v sense , larger values of r in will lower power dissipation in the lt6118 due to the reduction in i out while smaller values of r in will result in faster response time due to the increase in i out . if low sense currents must be resolved accurately in a system that has a ver y wide dynamic range, a smaller r in may be used if the maximum i outa current is limited in another way, such as with a schottky diode across r sense (figure 3). this will reduce the high current measurement accuracy by limiting the result, while increasing the low current measurement resolution. figure 3. shunt diode limits maximum input voltage to allow better low input resolution without overranging d sense r sense v + load 6118 f03 this approach can be helpful in cases where occasional bursts of high currents can be ignored. care should be taken when designing the board layout for r in , especially for small r in values. all trace and inter - connect resistances will increase the effective r in value, causing a gain error. the power dissipated in the sense resistor can create a thermal gradient across a printed circuit board and con - sequently a gain error if r in and r out are placed such that they operate at different temperatures. if signifcant power is being dissipated in the sense resistor then care should be taken to place r in and r out such that the gain error due to the thermal gradient is minimized. selection of external output gain resistor, r out the output resistor, r out , determines how the output cur - rent is converted to voltage. v out is simply i outa ? r out . typically, r out is a combination of resistors confgured as a resistor divider which has a voltage tap going to the comparator input to set the comparator threshold. in choosing an output resistor, the maximum output volt - age must frst be considered. if the subsequent circuit is a buffer or adc with limited input range, then r out must be chosen so that i outa(max) ? r out is less than the allowed maximum input range of this circuit. lt6118 6118f
12 for more information www.linear.com/lt6118 a pplica t ions i n f or m a t ion in addition, the output impedance is determined by r out . if another circuit is being driven, then the input impedance of that circuit must be considered. if the subsequent circuit has high enough input impedance, then almost any use - ful output impedance will be acceptable. however, if the subsequent cir cuit has relatively low input impedance, or draws spikes of current such as an adc load, then a lower o utput impedance may be required to preserve the accuracy of the output. more information can be found in the output filtering section. as an example, if the input impedance of the driven circuit, r in(driven) , is 100 times r out , then the accuracy of v out will be reduced by 1% since: v out = i outa ? r out ?r in(driven) r out + r in(driven) = i outa ?r out ? 100 101 = 0.99 ?i outa ?r out amplifer error sources the current sense system uses an amplifer and resistors to apply gain and level-shift the result. consequently, the output is dependent on the characteristics of the amplifer, such as gain error and input offset, as well as the matching of the external resistors. ideally, the circuit output is: v out = v sense ? r out r in ; v sense = r sense ?i sense in this case, the only error is due to external resistor mismatch, which provides an error in gain only. however, offset voltage, input bias current and fnite gain in the amplifer can cause additional errors: output voltage error, ?v out(vos) , due to the amplifer dc offset voltage, v os ? v out(vos) = v os ? r out r in the dc offset voltage of the amplifer adds directly to the value of the sense voltage, v sense . as v sense is increased, accuracy improves. this is the dominant error of the system and it limits the available dynamic range. output voltage error, ?v out(ibias) , due to the bias currents i b + and i b C the amplifer bias current i b + fows into the senselo pin while i b C fows into the sensehi pin. the error due to i b is the following: ? v out(ibias) = r out i b + ? r sense r in Ci b C ? ? ? ? ? ? since i b + i b C = i bias , if r sense << r in then, ?v out(ibias) = Cr out (i bias ) it is useful to refer the error to the input: ?v vin(ibias) = Cr in (i bias ) for instance, if i bias is 100na and r in is 1k, the input re - ferred error is 100v. this error becomes less signifcant as the value of r in decreases. the bias current error can be reduced if an external resistor, r in + , is connected as shown in figure 4, the error is then reduced to: v out(ibias) = r out ? i os ; i os = i b + C i b C minimizing low current errors will maximize the dynamic range of the circuit. figure 4. r in + reduces error due to i b sensehi lt6118 i sense r sense v + 7 v ? 4 v + r in v batt senselo 8 1 outa 6 6118 f04 r out v out r in + ? + output voltage error, ?v out(gain error) , due to external resistors the lt6118 exhibits a very low gain error. as a result, the gain error is only signifcant when low tolerance resistors are used to set the gain. note the gain error is systematically negative. for instance, if 0.1% resistors are used for r in and r out then the resulting worst-case gain error is C0.4% with r in = 100. figure 5 is a graph lt6118 6118f
13 for more information www.linear.com/lt6118 a pplica t ions i n f or m a t ion can be multiplied by the ja value, 163c/w for the ms8 package or 64c/w for the dfn, to fnd the maximum expected die temperature. proper heat sinking and thermal relief should be used to ensure that the die temperature does not exceed the maximum rating. le pin the le pin is used to enable the comparator output latch. when the le pin is high, the output latch is enabled and the comparator output will stay low once it is tripped. when le is low, the comparator output latch is disabled and the comparator operates transparently. to continuously operate the comparator transparently, the le pin should be grounded. do not leave the le pin foating. power-on reset during startup the state of the comparator output can - not be guaranteed. to guarantee the correct state of the comparator output on startup, a power-on reset (por) is required. a por can be implemented by holding the le pin low until the l t6118 is in such a state that the compara - tor output is stable. this can be achieved by using an rc network between the le, v + and gnd as shown in figure 6. when power is applied to the lt6118, the rc network causes the voltage on the le pin to remain below the v il (0.5v) threshold long enough for the comparator output to settle into the correct state. the le pin should remain below 0.5v for at least 100s after power up in order to guarantee a valid comparator output. the rc value can be determined with the following equation: rc = t ln v + v + C 0.5v ? ? ? ? ? ? ; t 100s figure 5. gain error vs resistor tolerance resistor tolerance (%) 0.01 0.01 resulting gain error (%) 0.1 1 10 0.1 1 10 6118 f05 r in = 100 r in = 1k of the maximum gain error which can be expected versus the external resistor tolerance. output current limitations due to power dissipation the lt6118 can deliver a continuous current of 1ma to the outa pin. this current fows through r in and enters the current sense amplifer via the sensehi pin. the power dissipated in the lt6118 due to the output signal is: p out = (v sensehi C v outa ) ? i outa since v sensehi v + , p outa (v + C v outa ) ? i outa there is also power dissipated due to the quiescent power supply current: p s = i s ? v + the comparator output current fows into the comparator output pin and out of the v C pin. the power dissipated in the lt6118 due to the comparator is often insignifcant and can be calculated as follows: p outc = (v outc C v C ) ? i outc the total power dissipated is the sum of these dissipations: p total = p outa + p outc + p s at maximum supply and maximum output currents, the total power dissipation can exceed 150mw. this will cause signifcant heating of the lt6118 die. in order to prevent damage to the lt6118, the maximum expected dissipa - tion in each application should be calculated. this number figure 6. rc network achieves power-on reset 6118 f06 v le le v + lt6118 r 110k 60v c 0.1f lt6118 6118f
14 for more information www.linear.com/lt6118 sensehi lt6118 i sense r sense v + 7 6 v ? 4 v + r in v batt senselo 8 1 outa 6118 f08 r out v out ? + a pplica t ions i n f or m a t ion output filtering the ac output voltage, v out , is simply i outa ? z out . this makes fltering straightforward. any circuit may be used which generates the required z out to get the desired flter response. for example, a capacitor in parallel with r out will give a lowpass response. this will reduce noise at the output, and may also be useful as a charge reservoir to keep the output steady while driving a switching circuit such as a mux or adc. this output capacitor in parallel with r out will create an output pole at: f C3db = 1 2 ? ?r out ?c l senselo, sensehi range the difference between v batt (see figure 8) and v + , as well as the maximum value of v sense , must be considered to ensure that the senselo pin doesnt exceed the range listed in the electrical characteristics table. the senselo and sensehi pins of the lt6118 can function from 0.2v above the positive supply to 33v below it. these operat - ing voltages are limited by internal diode clamps shown in figures 1 and 2. on supplies less than 35.5v , the lower range is limited by v C + 2.5v. this allows the monitored supply, v batt , to be separate from the lt6118 positive figure 8. v + powered separately from load supply (v b att ) figure 9. allowable senselo, sensehi voltage range 60 27 allowable operating voltage on senselo and senshi inputs (v) 2.8 10 20 20.2v 40.2v 30 40 50 2.5 2.7 10 20 30 40 50 35.5 v + (v) 60 6118 f09 valid senselo/ sensehi range figure 7. minimum resistance for three typical capacitor values supply voltage (v) 1 10 100 resistor value () 6118 f07 c = 100nf c = 10nf c = 1nf 100,000,000 10,000,000 1,000,000 100,000 10,000 1000 supply as shown in figure 8. figure 9 shows the range of operating voltages for the senselo and sensehi inputs, for different supply voltage inputs (v + ). the senselo and sensehi range has been designed to allow the lt6118 to monitor its own supply current (in addition to the load), as long as v sense is less than 200mv. this is shown in figure 10. minimum output voltage the output of the lt6118 current sense amplifer can produce a non-zero output voltage when the sense voltage is zero. this is a result of the sense amplifer v os being forced across r in as discussed in the output voltage er - ror, ? v out(vos) section. figure 11 shows the effect of the input offset voltage on the transfer function for parts at the rc will need to be chosen based on the supply voltage of the circuit. figure 7 can be used to easily determine an appropriate rc combination for an applications supply voltage range. lt6118 6118f
15 for more information www.linear.com/lt6118 figure 10. supply current monitored with load figure 11. amplifer output voltage vs input sense voltage sensehi lt6118 i sense r sense v + 7 6 v ? 4 r in v batt senselo 8 1 outa 6118 f10 r out v out ? + input sense voltage (v) 0 output voltage (mv) 40 80 120 20 60 100 200 400 600 800 6118 f11 1000 1000 300 500 700 900 v os = ?200v g = 100 v os = 200v a pplica t ions i n f or m a t ion the typical performance characteristics are labeled with respect to the initial sense voltage. the speed is also affected by the external components. using a larger r out will decrease the response time, since v out = i outa ? z out where z out is the parallel combination of r out and any parasitic and/or load capacitance. note that reducing r in or increasing r out will both have the effect of increasing the voltage gain of the circuit. if the output capacitance is limiting the speed of the system, r in and r out can be decreased together in order to maintain the desired gain and provide more current to charge the output capacitance. the response time of the comparator is the sum of the propagation delay and the fall time. the propagation delay is a function of the overdrive voltage on the input of the comparator. a larger overdrive will result in a lower propaga - tion delay. this helps achieve a fast system response time to fault events. the fall time is affected by the load on the output of the comparator as well as the pull-up voltage. the l t6118 amplifer has a typical response time of 500ns and the comparators have a typical response time of 500ns. when confgured as a system, the amplifer output drives the comparator input causing a total system response time which is typically greater than that implied by the individually specifed response times. this is due to the overdrive on the comparator input being determined by the speed of the amplifer output. internal reference and comparator the integrated precision reference and comparator com - bined with the high precision current sense allow for rapid and easy detection of abnormal load currents. this is often critical in systems that require high levels of safety and reliability . the l t6118 comparator is optimized for fault detection and is designed with a latching output. the latch - ing output prevents faults from clearing themselves and requires a separate system or user to reset the output. in applications where the comparator output can inter vene and disconnect loads from the supply , a latched output is required to avoid oscillation. the latching output is also useful for detecting problems that are intermittent. in applications where a latching output is not desired the le pin can be tied low to disable the latch. the v os limits. with a negative offset voltage, zero input sense voltage produces an output voltage. with a positive offset voltage, the output voltage is zero until the input sense voltage exceeds the input offset voltage. neglect - ing v os , the output circuit is not limited by saturation of pull-down circuitry and can reach 0v. response time the lt6118 amplifer is designed to exhibit fast response to inputs for the purpose of circuit protection or current monitoring. this response time will be affected by the external components in two ways, delay and speed. if the output current is very low and an input transient occurs, there may be an increased delay before the output voltage begins to change. the typical performance characteristics show that this delay is short and it can be improved by increasing the minimum output current, either by increasing r sense or decreasing r in . note that lt6118 6118f
16 for more information www.linear.com/lt6118 the comparator has one input available externally. the other comparator input is connected internally to the 400mv precision reference. the input threshold (the voltage which causes the output to transition from high to low) is designed to be equal to that of the reference. the reference voltage is established with respect to the device v C connection. comparator input the comparator input can swing from v C to 60v regardless of the supply voltage used. the input current for inputs well above the threshold is just a few pas. with decreas - ing input voltage, a small bias current begins to be drawn out of the input near the threshold, reaching 50na max when at ground potential. note that this change in input bias current can cause a small nonlinearity in the outa transfer function if the comparator input is coupled to the amplifer output with a voltage divider. for example, if the maximum comparator input current is 50na, and the resistance seen looking out of the comparator input is 1k, then a change in output voltage of 50v will be seen on the analog output when the comparator input voltage passes through its threshold. a pplica t ions i n f or m a t ion setting comparator threshold the comparator has an internal 400mv precision reference. in order to set the trip point of the lt6118 comparator as confgured in figure 12, the input sense voltage at which the comparator will trip, v sense(trip) must be calculated: v sense(trip) = i sense(trip) ? r sense the selection of r in is discussed in the selection of exter - nal input gain resistor r in section. once r in is selected, r out can be calculated: r out = r in 400mv v sense(trip) since the amplifer output is connected directly to the comparator input, the gain from v sense to v out is: a v = 400mv v sense(trip) as shown in figure 13, r2 can be used to increase the gain from v sense to v out without changing v sense(trip) . as before, r1 can be easily calculated: r1 = r in 400mv v sense(trip) outa i outa ? + v + c1 sensehi inc 6 7 8 5 6118 f12 v + v + v ? lt6118 senselo le outc 1 2 3 4 v le r c v pullup load v supply v sense r sense overcurrent flag r in + ? v ? i sense = v sense r sense r out c l v out 400mv reference c lc ? + figure 12. basic comparator confguration lt6118 6118f
17 for more information www.linear.com/lt6118 a pplica t ions i n f or m a t ion figure 13: comparator confguration with increased a v outa i outa ? + v + c1 sensehi inc 6 7 8 5 6118 f13 v + v + v ? lt6118 senselo le outc 1 2 3 4 v le r c v pullup load v supply v sense r sense overcurrent flag r in + ? v ? i sense = v sense r sense r1 r2 c l v out 400mv reference c lc ? + the gain is now: a v = r1 + r2 r in this gain equation can be easily solved for r2: r2 = a v ? r in C r1 if the confguration of figure 10 gives too much gain, r2 can be used to reduce the gain without changing v sense(trip) as shown in figure 14. a v can be easily calculated: a v = r1 r in figure 14: comparator confguration with reduced a v outa i outa ? + v + c1 sensehi inc 6 7 8 5 6118 f14 v ? v + v + v ? lt6118 senselo le outc 1 2 3 4 v le r c v pullup load v supply v sense r sense overcurrent flag r in + ? i sense = v sense r sense r1 r2 c l v out 400mv reference c lc ? + lt6118 6118f
18 for more information www.linear.com/lt6118 figure 15. comparator output transfer characteristics this gain equation can be easily solved for r1: r1 = a v ? r in the value of r2 can be calculated: r2 = 400mv ?r in C v sense(trip) ?r1 v sense(trip) hysteresis the comparator has a typical built-in hysteresis of 10mv to simplify design, ensure stable operation in the pres - ence of noise at the input, and to reject supply noise that might be induced by state change load transients. the hysteresis is designed such that the threshold voltage is altered when the output is transitioning from low to high as is shown in figure 15. a pplica t ions i n f or m a t ion external positive feedback circuitry can be employed to increase the effective hysteresis if desired, but such circuitry will have an effect on both the rising and fall - ing input thresholds, v th (the actual internal threshold remains unaffected). figure 16 shows how to add additional hysteresis to the comparator. r5 can be calculated from the amplifer output current which is required to cause the comparator output to trip, i over . r5 = 400mv i over , assuming r1 + r2 ( ) >> r5 to ensure (r1 + r2) >> r5, r1 should be chosen such that r1 >> r5 so that v outa does not change signifcantly when the comparator trips. r3 should be chosen to allow suffcient v ol and compara - tor output rise time due to capacitive loading. r2 can be calculated: r2 = r1? v dd C 390mv v hys(extra) ? ? ? ? ? ? figure 16. inverting comparator with added hysteresis ? + v + v + v ? inc v ? 4 6118 f16 outa 6 7 5 v + v + sensehi lt6118 r in r sense i load v + senselo outc3 1 8 400mv reference r3 r4 r5 r1 vth r2 v dd ? + v hys outc v th increasing v inc 6118 f15 lt6118 6118f
19 for more information www.linear.com/lt6118 note that the hysteresis being added, v hys(extra) , is in addition to the typical 10mv of built-in hysteresis. for very large values of r2 pcb related leakage may become an issue. a tee network can be implemented to reduce the required resistor values. the approximate total hysteresis is: v hys = 10mv + r1? v dd C 390mv r2 ? ? ? ? ? ? for example, to achieve i over = 900a with 50mv of total hysteresis, r5 = 442. choosing r1 = 4.42k, r3 = 10k and v dd = 5v results in r2 = 513k. the analog output voltage will also be affected when the comparator trips due to the current injected into r5 by the positive feedback. because of this, it is desirable to have (r1 + r2) >> r5. the maximum v outa error caused by this can be calculated as: ? v outa = v dd ? r5 r1 + r2 + r5 ? ? ? ? ? ? in the previous example, this is an error of 4.3mv at the output of the amplifer or 43v at the input of the amplifer assuming a gain of 100. since the comparator can be used independently of the current sense amplifer, it is useful to know the threshold voltage equations with additional hysteresis. the input rising edge threshold which causes the output to transi - tion from high to low is: v th r ( ) = 400mv ? 1 + r1 r2 ? ? ? ? ? ? a pplica t ions i n f or m a t ion the input falling edge threshold which causes the output to transition from low to high is: v th f ( ) = 390mv 1 + r1 r2 ? ? ? ? ? ? C v dd r1 r2 ? ? ? ? ? ? comparator output the comparator output can maintain a logic-low level of 150mv while sinking 500a. the output can sink higher currents at elevated v ol levels as shown in the typical performance characteristics. load currents are conducted to the v C pin. the output off-state voltage may range between 0v and 60v with respect to v C , regardless of the supply voltage used. reverse-supply protection the lt6118 is not protected internally from external rever - sal of supply polarity. to prevent damage that may occur during this condition, a schottky diode should be added in series with v C (figure 17). this will limit the reverse current through the lt6118. note that this diode will limit the low voltage operation of the lt6118 by effectively reducing the supply voltage to the part by v d . also note that the comparator reference, comparator out - put and le input are referenced to the v C pin. in order to preserve the precision of the reference and to avoid driving the comparator inputs below v C , r2 must connect to the v C pin. this will shift the amplifer output voltage up by v d . v outa can be accurately measured differentially across r1 and r2. the comparator output low voltage will also be shifted up by v d . the le pin threshold is referenced to the v C pin. in order to provide valid input levels to the lt6118 and avoid driving le below v C the negative supply of the driving circuit should be tied to v C of the lt6118. lt6118 6118f
20 for more information www.linear.com/lt6118 a pplica t ions i n f or m a t ion ? + v + v + v ? inc v ? 4 v d + ? v outa + ? 6118 f17 outa 6 7 5 v + v + sensehi lt6118 r in r sense i load v dd v dd senselo outc3 le 2 1 8 400mv reference r3 r1 r2 v dd ? + figure 17. schottky prevents damage during supply reversal typical a pplica t ions electronic fuse with power-on reset sensehi senselo outa 0.1 r10 100 lt6118 v ? to load v out 9.53k 475 0.8a overcurrent detection inc v + le 6 1 5 4 outc 8 7 10k 100k 6.2v* irf9640 2 5v 3 v le 6118 ta02 100k 2n7000 *cmh25234b 10f 24.9k 12v 100nf the electronic fuse can be reset either by pulling le line low or by cycling the power to the system. the circuit is designed to have a 100s power-on period. after power, while le is still below the threshold, the comparator is kept transparent to allow for initial inrush current. lt6118 6118f
21 for more information www.linear.com/lt6118 typical a pplica t ions mcu interfacing with hardware interrupts sensehi senselo outa 0.1 v + 100 lt6118 v ? to load v out adc in 8.66k 1.33k inc v + le outc 6 1 5 4 8 7 2 3 v le 6118 ta03 10k 5v v out /adc in atmega1280 pb0 pb1 pcint2 pcint3 adc2 pb5 5 6 7 2 3 1 overcurrent routine reset comparator mcu interupt outc goes low 5v 0v 6118 ta03b example: the comparator is set to have a 300ma overcurrent threshold. the mcu will receive the comparator output as a hardware interrupt and immediately run an appropriate fault routine. simplifed dc motor torque control the fgure above shows a simplifed dc motor control circuit. the circuit controls motor current, which is pro - portional to motor torque; the lt6118 is used to provide current feedback to an integrator that ser vos the motor current to the current set point. the l tc ? 6992 is used to convert the output of the difference amp to the motors pwm control signal. sensehi senselo outa 8 1 6 5 7 2 3 4 lt6118 v ? 9k 100k 2 3 7 ltc6246 4 6 1 3 6 irf640 5v 1n5818 0.1 v motor 5 4 2 0.47f v out current set point (0v to 5v) 1k 1m 6118 ta04 1k 78.7k 100k 280k inc v + le outc v le 100f + ? ltc6992-1 v + gnd 5v 1f brushed dc motor (0a to 5a) mabuchi rs-540sh mod set out div lt6118 6118f
22 for more information www.linear.com/lt6118 p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. msop (ms8) 0213 rev g 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev g) lt6118 6118f
23 for more information www.linear.com/lt6118 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (2 sides) 2.00 0.10 (2 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.75 0.05 r = 0.115 typ r = 0.05 typ 1.35 ref 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dcb8) dfn 0106 rev a 0.23 0.05 0.45 bsc pin 1 notch r = 0.20 or 0.25 45 chamfer 0.25 0.05 1.35 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.10 0.05 0.70 0.05 3.50 0.05 package outline 0.45 bsc 1.35 0.10 1.35 0.05 1.65 0.10 1.65 0.05 dcb package 8-lead plastic dfn (2mm 3mm) (reference ltc dwg # 05-08-1718 rev a) lt6118 6118f
24 for more information www.linear.com/lt6118 ? linear technology corporation 2014 lt 0414 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt6118 r ela t e d p ar t s typical a pplica t ion adc driving application part number description comments lt1787 bidirectional high side current sense amplifer 2.7v to 60v, 75v offset, 60a quiescent, 8v/v gain ltc4150 coulomb counter/battery gas gauge indicates charge quantity and polarity lt6100 gain-selectable high side current sense amplifer 4.1v to 48v, gain settings: 10, 12.5, 20, 25, 40, 50v/v ltc6101 high voltage high side current sense amplifer up to 100v, resistor set gain, 300v offset, sot-23 ltc6102 zero drift high side current sense amplifer up to 100v, resistor set gain, 10v offset, msop8/dfn ltc6103 dual high side current sense amplifer 4v to 60v, resistor set gain, 2 independent amps, msop8 ltc6104 bidirectional high side current sense amplifer 4v to 60v, separate gain control for each direction, msop8 lt6105 precision rail-to-rail input current sense amplifer C0.3v to 44v input range, 300v offset, 1% gain error lt6106 low cost high side current sense amplifer 2.7v to 36v, 250v offset, resistor set gain, sot-23 lt6107 high temperature high side current sense amplifer 2.7v to 36v, C55c to 150c, fully tested: C55c, 25c, 150c lt6109 high side current sense amplifer with reference and comparators with shutdown 2.7v to 60v, 125v, resistor set gain, 1.25% threshold error lt6700 dual comparator with 400mv reference 1.4v to 18v, 6.5a supply current lt6108 high side current sense amplifer with reference and comparator with shutdown 2.7v to 60v, 125v, resistor set gain, 1.25% threshold error lt6119 lt6109 without shutdown and por capability 2.7v to 60v, 200v, resistor set gain, 1.25% threshold error sensehi senselo outa 0.1 sense low sense high lt6118 v ? out 8.66k 0.1f 0.1f 1.33k inc v + le outc 6 1 5 4 8 7 2 3 v cc v ref v le 6118 ta05 in v cc 10k in + ltc2470 overcurrent comp to mcu 100 the low sampling current of the ltc2470 16-bit delta sigma adc is ideal for the lt6118. lt6118 6118f

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